1. Field of the Invention
The present invention is related generally to integrated circuits, and more specifically to a new device structure and process for preparing field effect transistors (FETs) having a drain junction offset.
2. Description of the Prior Art
Within microelectronic integrated circuits, transistors are used to perform many different functions. For example, within static random access memory (SRAM) devices, transistors are used to form memory cells to store bits of data. Within such memory cells, some transistors are used to actively pull-up the output of the memory cell.
The electrical characteristics of such an active pull-up transistor are important to the design and fabrication of multimegabit memory devices. One characteristic important in the design of such active pull-up transistors is the subthreshold leakage, or "off" current, which passes through the transistor when the transistor is biased in an "off" state. Transistors having a low subthreshold leakage current are desirable because they reduce power consumed while the memory device is in the standby mode.
In the design and manufacture of thin film transistors (TFTs), a drain junction offset is desirable to reduce such subthreshold leakage current. A drain junction offset exist when the drain junction is not located beneath the gate electrode, but instead is located a selected distance away from a point beneath the edge of the gate electrode.
In contrast, a source offset is not desirable because a source offset will reduce the transistor's on current.
Although self-aligned techniques to produce drain junction offset are known, they require excessive photo and etch steps to build a drain offset without a source offset.